The present invention relates generally to integrated circuits, and more particularly to level shifting between a core voltage and an I/O voltage on an integrated circuit.
The semiconductor industry is continually driven to reduce cost, reduce power, and improve performance (e.g., circuit speed) of integrated circuits (xe2x80x9cICxe2x80x9ds). Integrated circuit products include application specific integrated circuits (xe2x80x9cASICxe2x80x9ds), microprocessors, digital signal processors, memories, programmable logic, programmable controllers, and many other types of integrated circuits. Generally, price reduction is strongly driven by migrating products to scaled processes, which reduce die sizes and increase yields. Power reduction has generally been achieved by circuit design techniques, power management schemes, and parasitic scaling, among other factors. Performance improvement has generally resulted from design techniques, process enhancements, and parasitic scaling, among other factors.
Process technology continues to improve, resulting in the continual scaling and shrinking of device geometries, sizes and dimensions. Smaller devices generally require that operating voltages be scaled down to reduce the voltage differences across device components. Accordingly, operating voltages have been scaled from 5 volts down to 3.3 volts and further down to 1.8 volts, and generally will continue to decrease in the future (e.g., to 0.9 volts or less). This has resulted in the need for mixed-voltage-mode systems because not all components are scaled down at the same time. That is, integrated circuits may need to interface with various operating voltages as these and further voltage reductions are made. Currently, the industry generally provides products and printed circuit boards (PCBs) that may utilize 5 volt, 3.3 volt and 1.8 volt integrated circuits and devices. Generally, there may be a considerable transition period for the standard power supply to switch from a higher voltage level to a lower voltage level.
As an example, there is generally a current need in integrated circuits such as ASICs to transfer data between 1.8 volts in the core section of the device and 3.3 volts in the input/output (xe2x80x9cI/Oxe2x80x9d) section of the device. It takes a certain amount of time, however, to accomplish the voltage level shifts into and out of devices. As speed requirements generally continue to increase for these devices, there is an increasing need for IC designers and manufacturers to reduce the time taken by an IC to level shift a received signal, process it, and level shift it for output.
As an example, the timing specifications for the PCI-66 MHz computer bus were difficult for IC designers to meet, and now the timing specifications for the new PCI-X 133 MHz or 166 MHz computer buses appear to be extremely difficult to meet with prior art techniques. The PCI-133 MHz specification generally permits approximately 1 Gbyte/sec performance, which is double the bandwidth of the PCI-66 MHz specification. The PCI-X specification generally has very tight timing requirements for the I/O interface. For example, it requires a maximum of 1.2 ns for the setup time and a maximum of 3.8 ns for the clock-to-Q output delay in an ASIC. As indicated by Deepal Mehta, Advanced I/O Still Comes Up Short, ELECTRONIC ENGINEERING TIMES, May 22, 2000, at 103, there is generally a great need in the industry to meet this new specification because most major server, personal computer (xe2x80x9cPCxe2x80x9d), and PC board manufacturers desire to use devices with the faster PCI-X buffers.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention in which an integrated level shifting latch is used for integrated circuit I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. Preferably, the level shift and latch may be clocked on opposite phases of the clock. Also preferably, the level shift and latch may operate differentially on the data signal.
In accordance with a preferred embodiment of the present invention, an IC comprises a clocked level shifter, wherein the level shifter shifts data from a core voltage level to an I/O voltage level, and a clocked latch coupled an output of the level shifter, wherein the latch captures the data at the I/O voltage level. Preferably, the level shifter is a differential level shifter and the latch is a differential input latch receiving the data output from the level shifter. Also preferably, the level shift and the latch are accomplished on opposite phases of the clock.
In accordance with another preferred embodiment of the present invention, a method for providing data at an output of an IC comprises level shifting the data from a core voltage level to an I/O voltage level synchronous to an external clock, and latching the data at the I/O voltage level synchronous to the external clock. Preferably, the level shifting and the latching are performed differentially. Also preferably, the level shifting and latching are performed on opposite phases of the clock.
An advantage of a preferred embodiment of the present invention is that both setup and clock-to-Q times are significantly reduced with respect to prior art devices.
Another advantage of a preferred embodiment of the present invention is that higher speed industry specifications may be met. In particular, a preferred embodiment of the present invention may readily meet the PCI-X 133 MHz bus specifications, which are very difficult or even impossible to meet with prior art designs.
A further advantage of a preferred embodiment of the present invention is that fewer devices (e.g., transistors) are needed to implement the level shift and latch functions than in the prior art, thus saving valuable space on an integrated circuit.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.